(1) Field of the Invention
The invention relates to a method to form an integrated circuit device, and, more particularly, to a method to form an interconnecting structure for use in integrating multiple, RF and MMIC stackable modules.
(2) Description of the Prior Art
In the art of integrated circuits, electrical interconnection and packaging are key enabling technologies. Much recent work has been done to integrate multiple devices in three dimensions. That is, many universities and research institutes are now working on technologies to reduce the volume of and to improve the performance of integrated systems of multiple ICs. In this regard, silicon stacking and through wafer interconnects have been successfully demonstrated in the art. A stacked silicon system is one where multiple integrated circuit devices are vertically stacked, one upon another. Stacking circuit modules creates area efficiencies in the same way that a high rise office building is more land efficient than a single story building. A very complex function or group of functions can be integrated onto several ICs while taking a relatively small surface area of the system circuit board. Wafer through connects are a technique whereby holes are formed completely through the semiconductor substrate. Circuit signals from the top side of the integrated circuit can then be routed through the bulk of the substrate to the bottom side. This through interconnect, or through via, capability creates many packaging options to route signals in the vertical direction and, again, reduce the required surface area of the device or system.
A major limitation of the above-described approaches to three-dimensional integration is the high frequency performance of the resulting, vertically integrated system. The substrate bulk material is typically silicon having a relatively low resistance. The resistivity of the silicon substrate is well suited to the formation of surface level CMOS and bipolar devices. However, when high frequency signals are carried vertically through the bulk substrate, the low resistivity proves to be lossy and results in significant signal attenuation. For example, a conventional silicon substrate with a resistance of between about 5 Ohms and about 6 Ohms will cause a transmitted signal loss of about 0.5 dB for a 1 GHz signal that is passed from the top side of the substrate to the bottom side of the substrate using a through via. The high frequency or RF performance can be improved somewhat by increasing the resistance of the silicon or by replacing the silicon substrate with an insulator such as silicon dioxide. However, the RF performance is still not suitable for very high frequency devices or for multiple module, vertically stacked devices. The vertically passed signal simply interacts with the substrate too much and results in signal attenuation. In addition, the prior art techniques used for passing signals through the substrate exhibit poor impedance matching and therefore result in lossy RF performance.
Several prior art inventions relate to integrated circuit modules and packaging schemes and to through vias. U.S. Pat. No. 6,268,660 B1 to Dhong et al describes a method for multiple integrated circuit, module packaging. A silicon substrate has a plurality of through vias formed therein by drilling or by ultrasonic milling. Copper vias are then formed by plating and polishing. U.S. Pat. No. 5,656,553 to Leas et al discloses a method to form a multiple chip module by stacking die. Interconnection between die is made be forming a metal interconnect layer on a side surface of the stack. U.S. Pat. No. 5,587,119 to White shows a method to form a coaxial via in a substrate. An aperture is drilled through the substrate. A first conductor layer is formed to line the aperture and lies next to the substrate. The aperture is then filled by a dielectric layer. A smaller aperture is then drilled through the dielectric layer. The second aperture is then filled with a second conductor layer. International Patent Application WO 02/063686 A2 to Forbes et al teaches a method to form an integrated circuit with through holes having coaxial, inner and outer metal layers. U.S. Pat. No. 5,682,062 to Gaul demonstrates a method to form stacked, integrated circuit devices. International Patent Application WO 98/39781 to Gallagher et al teaches a method to form a multiple layer, printed circuit board. The prior art approaches have a major limitation. These approaches cannot provide controllable dielectric thicknesses within design requirements. However, the present invention provides controllable dielectric thicknesses between about 50 Å and about 500,000 Å depending on the design requirements.